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--- spo600:register [2024/04/16 18:10] – external edit 127.0.0.1
+++ spo600:register [2024/09/03 13:42] (current) – [Status Register] chris
@@ Line 17: / Line 17: @@
 ====  Status Register  ====
-A //status register// (or //Flag register//, or //Condition code register//) contains [[Flags|flag]] [[Word#Bit|bits]], which are set/cleared/tested either explicitly (by instructions) or implicitly (as the result of other operations). For example, the ARM AArch32 "Z" flag is set ("1") if an operation has a zero result, and cleared ("0") if an operation has a non-zero result. This flag is one bit within the Application Processor Status Register (APSR).
+A //status register// (or //Flag register//, or //Condition code register//) contains [[Word#Bit|bits]] holding individual [[Flags|flags]], which are set/cleared/tested either explicitly (by instructions) or implicitly (as the result of other operations). For example, the ARM AArch32 "Z" flag is set ("1") if an operation has a zero result, and cleared ("0") if an operation has a non-zero result. This flag is one bit within the Application Processor Status Register (APSR).
 ====  Control Registers  ====