spo600:instruction_set_architecture
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| spo600:instruction_set_architecture [2024/04/16 14:10] – external edit 127.0.0.1 | spo600:instruction_set_architecture [2024/05/08 07:39] (current) – external edit 127.0.0.1 | ||
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| - | ===== Instruction Set Architecture | + | ====== Instruction Set Architecture |
| The Instruction Set Architecture of a processor is the set of [[Instruction|instructions]] which that processor can execute, the [[Addressing Mode|addressing modes]] available, and the [[Instruction Encoding|encoding]] of those instructions as [[Machine Language|machine code]]. | The Instruction Set Architecture of a processor is the set of [[Instruction|instructions]] which that processor can execute, the [[Addressing Mode|addressing modes]] available, and the [[Instruction Encoding|encoding]] of those instructions as [[Machine Language|machine code]]. | ||
spo600/instruction_set_architecture.1713276609.txt.gz · Last modified: 2024/04/16 18:10 (external edit)