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--- spo600:instruction_encoding [2025/02/11 19:26] – chris
+++ spo600:instruction_encoding [2025/02/19 16:16] (current) – chris
@@ Line 9: / Line 9: @@
 The 6502 architecture uses variable-length byte sequences, from 1 to 3 bytes (including the [[OpCode|opcode]]) depending on the [[6502 Addressing Modes|addressing mode]].
-The x86_64 architecture uses variable-length byte sequences, from 1 to approximately 17 bytes.
+The x86_64 architecture uses variable-length byte sequences, from 1 to approximately 17 bytes. In addition to opcodes and arguments, the byte sequence may contain prefix bytes that alter the operation of the instruction or provide execution hints to the processor.
-The AArch64 architecture uses 32-bit long instructions. Since this instruction length is insufficient to adequately contain a 64-bit operand (such as an address), some operands are encoded using run-length encoding (RLE) or shifted-bitfield techniques. For certain operand values, it may be necessary to build the required value in a register with a few instructions. (The armv8 architecture also provides T32 mode (previously known as Thumb mode in armv7), which uses a mixed 32- and 16-bit instruction encoding to provide higher code density).
+The AArch64 architecture uses 32-bit long instructions. Since this instruction length is insufficient to adequately contain a 64-bit operand (such as an address), some operands are encoded using run-length encoding (RLE), relative addressing, or shifted-bitfield techniques. For certain operand values, it may be necessary to build the required value in a register with multiple instructions, such as an ''adrp'' followed by an ''add''. (The armv8 architecture also provides T32 mode (previously known as Thumb mode in armv7), which uses a mixed 32- and 16-bit instruction encoding to provide higher code density).